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| 0 R Spartan-II 2.5V FPGA Family: Introduction and Ordering Information 0 DS001-1 (v2.3) November 1, 2001 0 Preliminary Product Specification * System level features - SelectRAM+TM hierarchical memory: * 16 bits/LUT distributed RAM * Configurable 4K bit block RAM * Fast interfaces to external RAM - Fully PCI compliant - Low-power segmented routing architecture - Full readback ability for verification/observability - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with enable, set, reset - Four dedicated DLLs for advanced clock control - Four primary low-skew global clock distribution nets - IEEE 1149.1 compatible boundary scan logic Versatile I/O and packaging - Low cost packages available in all densities - Family footprint compatibility in common packages - 16 high-performance interface standards - Hot swap Compact PCI friendly - Zero hold time simplifies system timing Fully supported by powerful Xilinx development system - Foundation ISE Series: Fully integrated software - Alliance Series: For use with third-party tools - Fully automatic mapping, placement, and routing Introduction The SpartanTM-II 2.5V Field-Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The six-member family offers densities ranging from 15,000 to 200,000 system gates, as shown in Table 1. System performance is supported up to 200 MHz. Spartan-II devices deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined Virtex-based architecture. Features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The Spartan-II family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs). * Features * Second generation ASIC replacement technology - Densities as high as 5,292 logic cells with up to 200,000 system gates - Streamlined features based on Virtex architecture - Unlimited reprogrammability - Very low cost * Table 1: Spartan-II FPGA Family Members Logic Cells 432 972 1,728 2,700 3,888 5,292 System Gates (Logic and RAM) 15,000 30,000 50,000 100,000 150,000 200,000 CLB Array (R x C) 8 x 12 12 x 18 16 x 24 20 x 30 24 x 36 28 x 42 Total CLBs 96 216 384 600 864 1,176 Maximum Available User I/O (1) 86 132 176 196 260 284 Total Distributed RAM Bits 6,144 13,824 24,576 38,400 55,296 75,264 Total Block RAM Bits 16K 24K 32K 40K 48K 56K Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Notes: 1. All user I/O counts do not include the four global clock/user input pins. See details in Table 3, page 3. (c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS001-1 (v2.3) November 1, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 1 Spartan-II 2.5V FPGA Family: Introduction and Ordering Information R General Overview The Spartan-II family of FPGAs have a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked Loops (DLLs), one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. These functional elements are interconnected by a powerful hierarchy of versatile routing channels (see Figure 1). Spartan-II FPGAs are customized by loading configuration data into internal static memory cells. Unlimited reprogramming cycles are possible with this approach. Stored values in these cells determine logic functions and interconnections implemented in the FPGA. Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes. Spartan-II FPGAs are typically used in high-volume applications where the versatility of a fast programmable solution adds benefits. Spartan-II FPGAs are ideal for shortening product development cycles while offering a cost-effective solution for high volume production. Spartan-II FPGAs achieve high-performance, low-cost operation through advanced architecture and semiconductor technology. Spartan-II devices provide system clock rates up to 200 MHz. Spartan-II FPGAs offer the most cost-effective solution while maintaining leading edge performance. In addition to the conventional benefits of high-volume programmable logic solutions, Spartan-II FPGAs also offer on-chip synchronous single-port and dual-port RAM (block and distributed form), DLL clock drivers, programmable set and reset on all flip-flops, fast carry logic, and many other features. The Xilinx XC17S00A PROM family is recommended for serial configuration of Spartan-II FPGAs. The In-System Programmable (ISP) XC18V00 PROM family is recommended for parallel or serial configuration. DLL DLL BLOCK RAM CLBs CLBs BLOCK RAM CLBs CLBs DLL I/O LOGIC XC2S15 BLOCK RAM DLL DS001_01_091800 Figure 1: Basic Spartan-II Family FPGA Block Diagram 2 www.xilinx.com 1-800-255-7778 DS001-1 (v2.3) November 1, 2001 Preliminary Product Specification BLOCK RAM R Spartan-II 2.5V FPGA Family: Introduction and Ordering Information Spartan-II Product Availability Table 2 shows the package and speed grades available for Spartan-II family devices. Table 3 shows the maximum user I/Os available on the device and the number of user I/Os available for each device/package combination. The four Table 2: Spartan-II Package and Speed Grade Availability Pins Type Device XC2S15 Code -5 -6 XC2S30 -5 -6 XC2S50 -5 -6 XC2S100 -5 -6 XC2S150 -5 -6 XC2S200 -5 -6 100 Plastic VQFP VQ100 C, I C C, I C 144 Plastic TQFP TQ144 C, I C C, I C C, I C C, I C 144 Chip Scale BGA CS144 C, I C C, I C 208 Plastic PQFP PQ208 C, I C C, I C C, I C C, I C C, I C 256 Fine Pitch BGA FG256 C, I C C, I C C, I C C, I C 456 Fine Pitch BGA FG456 C, I C C, I C C, I C global clock pins are usable as additional user I/Os when not used as a global clock pin. These pins are not included in user I/O counts. Notes: 1. C = Commercial, TJ = 0 to +85C; I = Industrial, TJ = -40C to +100C. Table 3: Spartan-II User I/O Chart (1) Maximum User I/O 86 132 176 196 260 284 Available User I/O According to Package Type VQ100 60 60 TQ144 86 92 92 92 CS144 86 92 PQ208 132 140 140 140 140 FG256 176 176 176 176 FG456 196 260 284 Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Notes: 1. All user I/O counts do not include the four global clock/user input pins. DS001-1 (v2.3) November 1, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 3 Spartan-II 2.5V FPGA Family: Introduction and Ordering Information R Ordering Information Example: Device Type Speed Grade XC2S50 -6 PQ 208 C Temperature Range Number of Pins Package Type Device Ordering Options Device XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Speed Grade -5 Standard Performance -6 Higher Performance Number of Pins / Package Type VQ100 100-pin Plastic Very Thin QFP CS144 TQ144 FG256 FG456 144-ball Chip-Scale BGA 144-pin Plastic Thin QFP 256-ball Fine Pitch BGA 456-ball Fine Pitch BGA Temperature Range (TJ ) C = Commercial I = Industrial 0C to +85C -40C to +100C PQ208 208-pin Plastic QFP Revision History Version No. 2.0 2.1 2.2 2.3 Date 09/18/00 10/31/00 03/05/01 11/01/01 Description Sectioned the Spartan-II Family data sheet into four modules. Added industrial temperature range information. Removed Power down feature. Added statement on PROMs. Update Product Availability chart. Minor text edits. The Spartan-II Family Data Sheet DS001-1, Spartan-II 2.5V FPGA Family: Introduction and Ordering Information (Module 1) DS001-2, Spartan-II 2.5V FPGA Family: Functional Description (Module 2) DS001-3, Spartan-II 2.5V FPGA Family: DC and Switching Characteristics (Module 3) DS001-4, Spartan-II 2.5V FPGA Family: Pinout Tables (Module 4) PN 011311 4 www.xilinx.com 1-800-255-7778 DS001-1 (v2.3) November 1, 2001 Preliminary Product Specification |
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